1. Field of the Invention
The present invention relates to bus line receivers, and more particularly, to a receiver which meets the specifications for the Universal Serial Bus and that compensates for skew in the differential inputs.
2. Description of the Related Art
Referring to FIG. 1, there is illustrated a prior art Universal Serial Bus (USB) receiver 20. The USB standard specifies that the USB receiver 20 must have an input sensitivity of at least 200 mV when both differential data inputs DP, DM are in the range of at least 0.8 V to 2.5 V with respect to its local ground reference. The USB standard also specifies that a differential input receiver 22 must be used to accept the USB data input signals DP, DM, and that both inputs DP and DM must be zero to signal an end of packet (EOP) condition. The differential receiver 22 is used to detect the differential signal between the two inputs DP, DM, and two single-ended receivers 24, 26 for the two data input lines DP, DM, respectively, are used to detect the EOP condition.
The purpose of the single-ended receivers 24, 26 is to make outputs RXP, RXM both go to zero to signal the EOP condition. When both inputs DP, DM are driven with single-ended zero for two bits to indicate the EOP condition, outputs d.sub.1, d.sub.2 of the differential receiver 22 become undefined. The two single-ended receivers 24, 26 provide two bits of single-ended output (SEO) in the form of outputs d.sub.3, d.sub.4. The OR gate 28 is used to form an end of packet signal g which is ANDed with outputs d.sub.1, d.sub.2 via AND gates 30, 32. Without the single-ended receivers 24, 26 the outputs RXP, RXM are uncertain when the inputs DP, DM go to zero to signal the EOP condition. Thus, the single-ended receivers 24, 26 are used only for the EOP condition.
FIG. 2 illustrates the operation of the USB receiver 20 when there is no skew between the input signals DP and DM. Specifically, when there is no skew between input signals DP and DM, the rise time T.sub.R and fall time T.sub.F of inputs DP and DM are equal, which causes the inputs DP and DM to cross at the mid-point of their transition from high to low, and vise versa. In this scenario, the outputs d.sub.3 and d.sub.4 are not both low at the same time until input signals DP and DM both go low to signal the EOP condition. Thus, the end of packet signal g is held high until the EOP condition occurs, and as long as signal g is held high, the outputs d.sub.1 and d.sub.2 of the differential receiver 22 control the outputs RXP and RXM.
When the EOP condition is received, both inputs DP and DM go to zero and remain zero only during the EOP condition. This causes the outputs d.sub.1 and d.sub.2 to become uncertain, as illustrated by 34, 36, and therefore, the outputs d.sub.1 and d.sub.2 are unable to control the outputs RXP and RXM. This is where the single-ended receivers 24, 26 control. The single-ended receivers 24, 26 generate zeros at their respective outputs d.sub.3, d.sub.4 which cause the end of packet signal g to go low via OR gate 28. Because signal g is providing a zero to an input of the each of the AND gates 30, 32, both outputs RXP and RXM go to zero in accordance with the EOP condition.
One disadvantage of the USB receiver 20 is illustrated in FIG. 3. Specifically, if there is skew between the input signals DP and DM, or the rise time T.sub.R and fall time T.sub.F of the input signals DP and DM are different, distortion will be caused in the output g which will lead to distortion in outputs RXP and RXM. FIG. 3 shows that the input signal DP is skewed with respect to the input signal DM by an amount d.sub.sk. This causes the single-ended receivers 24, 26 to each be triggered at different times since they are each triggered at the switching threshold of only one of the signals DP and DM rather than the crossing point of the signals DP and DM. Unwanted glitch pulses 37 with a duration of d.sub.sk are produced in the end of packet signal g which distorts the output signals RXP and RXM by .+-.1/2 d.sub.sk. In other words, signal g goes low before an EOP condition is received, as indicated by the glitches 37, which in turn causes the outputs RXP and RXM to go low even though an EOP condition has not been received.
The data signal quality is degraded by the scheme shown in FIG. 1. Therefore, there is a need for a USB receiver which can compensate for skew and/or differing rise and fall times T.sub.R, T.sub.F between the differential inputs DP and DM.